1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing it, and more particularly to a semiconductor device having a ferroelectric layer and a method of manufacturing such a device.
2. Description of the Related Art
As a semiconductor device having a ferroelectric layer, a ferroelectric memory is previously known. FIGS. 14 and 15 partially show the sectional structure of a conventional ferroelectric memory. The ferroelectric memory includes a ferroelectric capacitor FC composed of a ferroelectric film FL and a lower electrode LE and an upper electrode UE sandwiching the ferroelectric film therebetween, a MOSFET, etc. The ferroelectric memory has been manufactured in the following manner.
First, as seen from FIG. 14, a field oxide film 4 for element isolation is formed on a semiconductor substrate 2. A MOSFET is formed within an element region encircled by the field oxide film 4. In this figure, an N.sup.+ diffused layer 6 (source regionor drain region) is present on a P-type Si substrate surface. On the N.sup.+ diffused layer 6, a ferroelectric capacitor FC is formed through an interlayer insulating film 8. The ferroelectric capacitor FC has a structure in which the lower electrode LE, ferroelectric layer FL and upper electrode UE are stacked in this order.
Contact holes 18a and 18b are formed in the interlayer insulating film 8. The contact hole 18a is formed so as to reach the N.sup.+ diffused layer 6. The contact hole 18b is formed to reach the upper electrode UE of the ferroelectric capacitor FC.
As seen from FIG. 15, on the resultant surface, a titanium (Ti) layer 10, a barrier metal layer 12 of titanium nitride (TiN), an aluminum wiring layer 14 and a passivation film 16 are formed. By carrying out any heating step after the Ti layer 10 is formed, only a contact portion 10a between the Ti layer 10 and the N.sup.+ diffused layer is silicified as silicide
This silicide portion serves to reduce the connection resistance between the Al wiring layer 14 and the N.sup.+ diffused layer 6.
However, the conventional ferroelectric memory has the following problems. It is known that the ferroelectric thin film does not exhibit ferroelectricity at a certain high temperature. The reason is not necessarily clear. When the ferroelectric material is further heated, it does not return to its original state. In short, the ferroelectric material looses the ferroelectricity non-reversibly at a certain temperature or higher.
For this reason, in order to avoid the deterioration of the ferroelectric layer FL, the heating temperature for silicifying cannot be risen so high. On the other hand, at such a temperature, the titanium material cannot be silicified sufficiently. Namely, the Ti layer 10 at the contact portion 10a is not silicified sufficiently. As a result, the contact portion 10a between the Ti layer 10 and the N.sup.+ diffused layer 6 has somewhat of property of a Schottky diode. Namely, the contact resistance does not become so low, and has also characteristic dependent on a voltage. This impede the high-speed response of the memory.
In order to solve such a problem, a technique of using a platinum (Pt) layer in place of the Ti layer 10 can be proposed. Since platinum is silicified at a lower temperature than titanium is, it can be silicified sufficiently at a temperature lower than the temperature when the ferroelectric layer FL is deteriorated.
However, since the platinum exhibits a strong reduction/catalysis function, if any step is thereafter effected within a reduction atmosphere, the reduction of the ferroelectric material which is an oxide is promoted owing to the presence of platinum not silicified. Thus, the ferroelectric material will be deteriorated. Therefore, after the silicifying step, the non-reacted platinum must be removed. However, the platinum cannot but be removed using aqua regia. It is difficult to effect such a step in a common semiconductor processing process.